Title :
Testability properties of BDDs
Author :
Marques, F. ; Correia, V. ; Prado, A. ; Lubaszewski, M. ; Reis, A.
Author_Institution :
Instituto de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
Abstract :
This paper discusses the relationship among BDDs (binary decision diagrams), unateness and redundancy. We show that redundancy is introduced in logic circuits when the general case (binate) of the Shannon decomposition is used for unate functions. As ROBDDs are not able to specify in their structure if a decomposition in a node or a group of nodes is unate, circuits derived from ROBDDs will contain redundancies. We also show that, in order to represent unateness using BDD structures, it is necessary to use BDDs in which variables are not ordered and read more than once. Based on these observations, we propose a new algorithm that is able to generate robustly-path-delay-testable circuits without increasing the delay, by removing redundancies directly on the BDD representation.
Keywords :
Boolean algebra; binary decision diagrams; design for testability; formal verification; logic design; logic simulation; logic testing; network analysis; redundancy; BDD redundancy removal algorithm; BDD structure unateness; BDD testability properties; BDD unateness/redundancy relationship; Boolean algebra; ROBDD unate node/node group; Shannon decomposition general binate case; binary decision diagrams; circuit delays; formal verification; graph based logic synthesis data structures; logic circuit redundancy; nonordered variables; robustly-path-delay-testable circuits; unate functions; variable reading frequency; Binary decision diagrams; Boolean functions; Circuit faults; Circuit synthesis; Data structures; Logic circuits; Logic testing; Redundancy; Robustness; Timing;
Conference_Titel :
Integrated Circuits and Systems Design, 2002. Proceedings. 15th Symposium on
Print_ISBN :
0-7695-1807-9
DOI :
10.1109/SBCCI.2002.1137641