Title :
Reducing test application time through interleaved scan
Author :
Corno, F. ; Reorda, M. Sonza ; Squillero, G.
Author_Institution :
Dipt. di Automatica e Informatica, Politecnico di Torino, Italy
Abstract :
This paper proposes a new method for reducing the test length for digital circuits by adopting an architecture derived from the popular scan approach. An evolutionary optimization algorithm is exploited to find the optimal solution. The proposed approach was tested on the ISCAS89 standard benchmarks and the experimental results show its effectiveness.
Keywords :
automatic test pattern generation; automatic test software; boundary scan testing; circuit testing; fault location; genetic algorithms; logic testing; performance evaluation; ATPG; ISCAS89 benchmark testing; automatic test pattern generator; digital circuit interleaved scan test; evolutionary optimization algorithms; genetic algorithms; logic testing; scan test architecture; test application time reduction; test length reduction; Automatic test pattern generation; Automatic testing; Benchmark testing; Circuit faults; Circuit testing; Digital circuits; Fault detection; Hardware; Sequential analysis; Test pattern generators;
Conference_Titel :
Integrated Circuits and Systems Design, 2002. Proceedings. 15th Symposium on
Print_ISBN :
0-7695-1807-9
DOI :
10.1109/SBCCI.2002.1137642
