Analyzing area and performance penalty of protecting different digital modules with Hamming code and triple modular redundancy

This work compares two fault tolerance techniques, Hamming code and triple modular redundancy (TMR), that are largely used to mitigate single event upsets in integrated circuits, in terms of area and performance penalty. Both techniques were implemented in VHDL and tested in two target applications: arithmetic circuits with pipeline and registers files. Area overhead results show that TMR is more appropriated for modules using single registers like in pipelines, control and datapath circuits, while Hamming code is a better trade-off for groups of registers, such as register files, caches and embedded memories.