A methodology for dynamic power consumption estimation using VHDL descriptions

Author

Alcântara, João M S ; Vieira, Antônio C C ; Durand, Federico GálvezGå ; Alves, Vladimir Castro

fYear

2002

fDate

2002

Firstpage

149

Lastpage

154

Abstract

Power consumption became an important feature to be considered in system implementations. This work presents a methodology for dynamic power consumption estimation using hardware descriptions written in VHDL; a library with information for transitions and power consumption for all components of the target library is created. A case study for the KASUMI cryptographic algorithm is reported. This algorithm was chosen to compose the 3rd Generation Partnership Project (3GPP) security functions for mobile systems. Restrictions imposed by the 3GPP to the hardware implementation of the KASUMI cryptographic algorithm were analyzed and satisfied; our dynamic power consumption estimation methodology is used. Only CMOS technologies are discussed in this paper.

Keywords

3G mobile communication; CMOS digital integrated circuits; VLSI; cryptography; hardware description languages; integrated circuit design; logic CAD; parameter estimation; 3GPP security functions; 3rd Generation Partnership Project security functions; CMOS technology; KASUMI cryptographic algorithm; VHDL descriptions; VHDL library; dynamic power consumption estimation; hardware descriptions; hardware implementation; mobile systems; power consumption; system implementations; target library components; transition information; CMOS digital integrated circuits; CMOS logic circuits; CMOS technology; Cryptography; Electrical capacitance tomography; Energy consumption; Information security; Iron; Linear predictive coding; Power system security;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design, 2002. Proceedings. 15th Symposium on

Print_ISBN

0-7695-1807-9

Type

conf

DOI

10.1109/SBCCI.2002.1137651

Filename

1137651