A new FGMOS active resistor with improved linearity and frequency response

Author

Popa, C.

Author_Institution

Fac. of Electron. & Telecommun., Univ. Politehnica of Bucharest, Romania

Volume

2

fYear

2004

fDate

4-6 Oct. 2004

Firstpage

295

Abstract

A new linearity improvement technique for a CMOS active resistor is presented. In order to minimize the silicon area, an original method based on the utilization of FGMOS (floating gate MOS) transistors and on an optimal implementation of the current-controlled voltage generators from the active resistor circuit is designed, having the result of about two order of magnitude reducing area with respect to a classical resistor. A new idea for minimizing the errors introduced by the second-order effects is further presented. The circuit estimated linearity error is under 1% for an extended input range. The active resistor is designed for low-voltage low-power application and it is implemented in 0.35 μm CMOS technology.

Keywords

CMOS integrated circuits; MOSFET circuits; frequency response; integrated circuit design; linearisation techniques; power MOSFET; resistors; 0.35 micron; CMOS active resistor; CMOS technology; circuit area reduction; circuit linearity degradation; complementary metal-oxide-semiconductor; current controlled voltage generators; error minimisation; floating gate MOS transistors; frequency response; improved linearity; low voltage low power application; second order effects; Capacitance; Circuits; Frequency response; Linearity; MOS devices; MOSFETs; Resistors; Silicon; Surface resistance; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Conference, 2004. CAS 2004 Proceedings. 2004 International

Print_ISBN

0-7803-8499-7

Type

conf

DOI

10.1109/SMICND.2004.1402998

Filename

1402998