Core communication interface for FPGAs

Author

Palma, José Carlos ; De Mello, Aline Vieira ; Möller, Leandro ; Moraes, Fernando ; Calazans, Ney

Author_Institution

Pontificia Univ. Catolica do Rio Grande do Sul, Porto Alegre, Brazil

fYear

2002

fDate

2002

Firstpage

183

Lastpage

188

Abstract

The use of pre-designed and pre-verified hardware modules, also called IP cores, is an important part of the effort to design and implement complex systems. However, many aspects of IP core manipulation are still to be developed. This paper presents an approach to solve problems related to the dynamic interconnection of hard IP cores. The approach targets system-on-a-chip designs build in a single FPGA device. The paper proposes a communication interface that allows IP core replacement during FPGA normal operation. The same interface also allows communication among distinct IP cores to take place.

Keywords

field programmable gate arrays; industrial property; integrated circuit design; integrated circuit interconnections; logic design; system-on-chip; FPGA; IP core manipulation; IP core replacement; IP cores; complex system design; core communication interface; dynamic interconnection; hard IP cores; pre-designed pre-verified hardware modules; single FPGA device; system-on-a-chip designs; Application software; Computer architecture; Field programmable gate arrays; Hardware; Integrated circuit interconnections; Integrated circuit technology; Logic; Software tools; System-on-a-chip; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design, 2002. Proceedings. 15th Symposium on

Print_ISBN

0-7695-1807-9

Type

conf

DOI

10.1109/SBCCI.2002.1137656

Filename

1137656