DocumentCode
2717861
Title
A low-cost FPGA implementation of the Advanced Encryption Standard algorithm
Author
Zigiotto, Anderson Cattelan ; D´Amore, Roberto
Author_Institution
Divisao de Engenharia Eletronica, Inst. Tecnologico de Aeronaut., Sao Jose de Campos, Brazil
fYear
2002
fDate
2002
Firstpage
191
Lastpage
196
Abstract
This work presents an architecture for a hardware implementation of the Rijndael block cipher with 128-bit key. Rijndael block cipher was recently adopted by the United States government as the new Advanced Encryption Standard (AES). The proposed architecture was designed for low-cost, mid-density FPGA.
Keywords
cryptography; field programmable gate arrays; integrated circuit design; logic design; telecommunication standards; 128 bit; AES; Advanced Encryption Standard algorithm; FPGA implementation; Rijndael block cipher; hardware implementation architecture; mid-density FPGA; Cryptography; Field programmable gate arrays;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuits and Systems Design, 2002. Proceedings. 15th Symposium on
Print_ISBN
0-7695-1807-9
Type
conf
DOI
10.1109/SBCCI.2002.1137657
Filename
1137657
Link To Document