Title :
A low-cost FPGA implementation of the Advanced Encryption Standard algorithm
Author :
Zigiotto, Anderson Cattelan ; D´Amore, Roberto
Author_Institution :
Divisao de Engenharia Eletronica, Inst. Tecnologico de Aeronaut., Sao Jose de Campos, Brazil
Abstract :
This work presents an architecture for a hardware implementation of the Rijndael block cipher with 128-bit key. Rijndael block cipher was recently adopted by the United States government as the new Advanced Encryption Standard (AES). The proposed architecture was designed for low-cost, mid-density FPGA.
Keywords :
cryptography; field programmable gate arrays; integrated circuit design; logic design; telecommunication standards; 128 bit; AES; Advanced Encryption Standard algorithm; FPGA implementation; Rijndael block cipher; hardware implementation architecture; mid-density FPGA; Cryptography; Field programmable gate arrays;
Conference_Titel :
Integrated Circuits and Systems Design, 2002. Proceedings. 15th Symposium on
Print_ISBN :
0-7695-1807-9
DOI :
10.1109/SBCCI.2002.1137657
