An IP of an Advanced Encryption Standard for Altera™ devices

This work presents an IP of the Rijndael encryption algorithm, the new Advanced Encryption Standard (AES) approved by the National Institute of Standards and Technology (NIST). The IP uses a VHDL description optimized to Altera devices. This Rijndael implementation runs its symmetric cipher algorithm using a key with 128 bits. This mode is called AES128. Two designs are proposed. The first one is a performance version, using full parallel operation and achieving an 820 Mbps throughput in an APEX device. The second and third designs present two costs×benefit approaches. The paper presents the Rijndael basic structures, the AES128 architecture and results of throughput and device utilization in Altera devices.