Pipelined entropy coders for JPEG compression

Author

Agostini, Luciano Volcan ; Silva, Ivan Saraiva ; Bampi, Sergio

Author_Institution

Fed. Univ. of Pelotas, Rio Grande Do Sul, Brazil

fYear

2002

fDate

2002

Firstpage

203

Lastpage

208

Abstract

This paper presents the proposal and design of architectures to be used in the final stage of JPEG compression: entropy coding. This paper focuses on the compression of gray scale images and color images. The entropy coder architectures were described in VHDL and were synthesized for an Altera Flex10kE FPGA. The entropy coder for gray scale images reaches a processing rate of 400 input matrices of 8×8 pixels per second and the entropy coder for color images reaches a processing rate of 357 matrices per second. This performance is larger than the performance demanded by real time applications and it encourages the use of the entropy coder architectures in a JPEG compressor designed in hardware.

Keywords

data compression; entropy codes; field programmable gate arrays; hardware description languages; image coding; image colour analysis; logic CAD; standards; Altera Flex10kE FPGA; JPEG compression; JPEG compressor; VHDL; color images; entropy coder architecture design; entropy coding; gray scale images; input matrices; pipelined entropy coders; processing rate; real time applications; Color; Discrete cosine transforms; Entropy coding; Field programmable gate arrays; Focusing; Hardware; Image coding; Microelectronics; Pixel; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design, 2002. Proceedings. 15th Symposium on

Print_ISBN

0-7695-1807-9

Type

conf

DOI

10.1109/SBCCI.2002.1137659

Filename

1137659