An offset self-correction sample and hold circuit for precise applications in low voltage CMOS

Author

Ferreira, Luís Henrique C ; Moreno, Robson L. ; Pimenta, Tales C. ; Filho, Carlos A R

Author_Institution

Microelectron. Group, Univ. Fed. de Itajuba, Brazil

fYear

2002

fDate

2002

Firstpage

243

Lastpage

246

Abstract

This work describes a new topology for CMOS sample-and-hold circuits, in low voltage, with self-correction of the offset voltage caused by mismatches in the differential input pair of the operational amplifier. The charge injection of the NMOS switches is an important factor and it is minimized in this topology. The results were obtained using the ACCUSIM II simulator on the AMS CMOS 0.8 μm CYE and they reveal the circuit has a reduced error of just 0.03% at the output.

Keywords

CMOS integrated circuits; MOSFET; circuit CAD; circuit simulation; integrated circuit design; integrated circuit modelling; low-power electronics; operational amplifiers; sample and hold circuits; 0.8 micron; 1 to 3 V; 100 kHz; 12 bit; 5 V; CMOS low-voltage offset self-correction S/H circuits; NMOS switch charge injection minimization; circuit output error reduction; design simulation; operational amplifier differential input pair offset voltage; sample and hold circuits; CMOS technology; Circuit topology; Low voltage; MOS devices; Microelectronics; Operational amplifiers; Sampling methods; Switched capacitor circuits; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design, 2002. Proceedings. 15th Symposium on

Print_ISBN

0-7695-1807-9

Type

conf

DOI

10.1109/SBCCI.2002.1137665

Filename

1137665