Automatic generation of digital cell libraries

Author

Togni, J. ; Schneider, F.R. ; Correia, V.P. ; Ribas, R.P. ; Reis, A.I.

Author_Institution

Instituto de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil

fYear

2002

fDate

2002

Firstpage

265

Lastpage

270

Abstract

This paper presents cell design flow - CDF, a tool for automatic generation of digital cell libraries. It is able to synthesize physical layouts of logic cells from truth table descriptions or Boolean equations. The tool is also able to generate a complete set of cells according to boundary conditions, such as the maximum number of cell inputs and the maximum number of serial transistors. The libraries provided by CDF are compatible to professional IC design environments, like Cadence and Mentor Graphics.

Keywords

Boolean functions; CMOS digital integrated circuits; circuit layout CAD; integrated circuit design; logic CAD; Boolean equations; CDF tool; CMOS topology; IC design environments; boundary conditions; cell design flow tool; digital cell library automatic generation tool; logic CAD; logic cell physical layout synthesis; maximum cell input number; maximum serial transistor number; truth table descriptions; Boolean functions; Boundary conditions; Circuits and systems; Design automation; Design methodology; Equations; Graphics; Logic functions; SPICE; Software libraries;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design, 2002. Proceedings. 15th Symposium on

Print_ISBN

0-7695-1807-9

Type

conf

DOI

10.1109/SBCCI.2002.1137669

Filename

1137669