A modeling and circuit reduction methodology for circuit simulation of DRAM circuits

As DRAM circuit densities increase and feature sizes decrease, circuit simulation of these circuits is becoming increasingly more critical and challenging in order to handle the large circuit capacity (millions of transistors), together with the accuracy required to take into account submicron effects. This paper presents a modeling and circuit reduction methodology and a DRAM modeling tool that lets the user configure the model architecture, parameterize and generate reduced macromodels, select and switch between different-level models, link the different models, and define circuit stimulus signals for the circuit simulation of the entire DRAM design