Embedded RAM testing

Author

Franklin, Manoj ; Saluja, Kewal K.

Author_Institution

Dept. of Electr. & Comput. Eng., Clemson Univ., SC, USA

fYear

1995

fDate

7-8 Aug 1995

Firstpage

29

Lastpage

33

Abstract

Embedded RAMs are RAMs whose address, data and read/write controls can not be directly controlled or observed through the chip´s I/O pins. Testing these memories, which are incorporated on a large percentage of VLSI devices, is naturally harder because of the lack of controllability of its inputs and observability of its outputs. Testing such RAMs is the theme of this paper. It brings to light the challenges involved in testing embedded RAMs, and discusses techniques such as design for testability (DFT) and built-in self test (BIST), which help in improving the testability of these RAMs

Keywords

VLSI; built-in self test; controllability; design for testability; integrated circuit testing; observability; random-access storage; real-time systems; VLSI devices; address controls; built-in self test; data controls; design for testability; embedded RAM testing; input controllability; output observability; read/write controls; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Design for testability; Logic testing; Pins; Random access memory; Read-write memory; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design and Testing, 1995., Records of the 1995 IEEE International Workshop on

Conference_Location

San Jose, CA

Print_ISBN

0-8186-7102-5

Type

conf

DOI

10.1109/MTDT.1995.518078

Filename

518078