DocumentCode
2718329
Title
Synchronization issues in SDH networks
Author
Zhou, Lianhong ; Wang, Xu ; Feng, Chongxi
Author_Institution
Dept. of Electron. Eng., Tsinghua Univ., Beijing, China
Volume
2
fYear
2000
fDate
2000
Firstpage
1033
Abstract
From the perspective of the history of network synchronization, the paper proposes several synchronization issues in SDH networks. The architecture of the SDH equipment clock (SEC) is also presented. The role and the implementation of desynchronizer, one of the SDH key components, is discussed in detail. Some points to be considered when designing a digital synchronization network are also outlined
Keywords
application specific integrated circuits; multiplexing equipment; synchronisation; synchronous digital hierarchy; ASIC HTP9021; SDH equipment clock architecture; SDH networks; desynchronizer; digital synchronization network; synchronization issues; Clocks; Communication networks; Communication switching; Frequency synchronization; History; Intelligent networks; Jitter; SONET; Synchronous digital hierarchy; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Communication Technology Proceedings, 2000. WCC - ICCT 2000. International Conference on
Conference_Location
Beijing
Print_ISBN
0-7803-6394-9
Type
conf
DOI
10.1109/ICCT.2000.890852
Filename
890852
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