Title :
Automatic computation of test length for pseudo-random memory tests
Author :
Van de Goor, Ad J.
Author_Institution :
Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
Abstract :
The increasing emphasis on reducing the defect level of shipped memory parts (current targets are 10 ppm) demand a very high fault coverage of memory tests. Deterministic tests have the advantage of a 100% fault coverage for the targeted faults. However, with each new technology, new layout and new fabrication process, new types of defects will show up; the probability of occurrence of these defects may vary during the time period these parts are produced. This demands for a test strategy whereby tests can be changed/added during the production process of the part. Pseudo-random tests are tests, applied externally or as a BIST, which can be parameterized (mainly via the test length) to detect newly discovered defects. The determination of the test length, for a given fault model, type of pseudo-random test and a given escape probability, is a very complex process. This paper describes a mechanism for automating this process
Keywords :
automatic testing; built-in self test; circuit analysis computing; integrated circuit testing; integrated memory circuits; probability; adaptable test strategy; automatic test length computation; built-in self-test; defect level reduction; defect occurrence probability; deterministic tests; escape probability; externally applied tests; fabrication process; fault coverage; fault model; layout; new defect types; new technology; newly discovered defects; pseudo-random memory tests; shipped memory parts; test parameterization; Automatic testing; Built-in self-test; Decoding; Logic; Performance evaluation; Production; SRAM chips; Semiconductor device modeling; Voltage;
Conference_Titel :
Memory Technology, Design and Testing, 1995., Records of the 1995 IEEE International Workshop on
Conference_Location :
San Jose, CA
Print_ISBN :
0-8186-7102-5
DOI :
10.1109/MTDT.1995.518082
