Performance evaluation of a three-stage packet switch with internal speedup and independent routing

The performance of a three-stage Clos-like packet switching fabric is evaluated. With the switching fabric architecture, the switching element of the first-stage and the third-stage both have shared memory buffering, and the switching element in the second-stage is bufferless. In order to achieve better performance/complexity characteristics, several operations are adopted: internal speedup, independent routing, and buffer backpressure control between switch interfaces and switching fabric. Under the uniform traffic model, the effect of speedup factor and buffer size on the performance of this switching fabric is analyzed, and some conclusions are given