DocumentCode
2718457
Title
Minimizing the number of paths in BDDs
Author
Fey, Görschwin ; Drechsler, Rolf
Author_Institution
Inst. of Comput. Sci., Bremen Univ., Germany
fYear
2002
fDate
2002
Firstpage
359
Lastpage
364
Abstract
BDDs are used in several fields as e.g. formal verification or synthesis. Minimizing the number of nodes in a BDD is a common technique, to reduce the memory needed to express a function. But recently applications like SAT-solving or synthesis have been shown to benefit from a small number of paths in a BDD. Here we present an algorithm and its implementation to carry out the minimization of a BDD with respect to the number of paths. After showing the existence of functions that can not be represented by a BDD that is minimal in the number of nodes and the number of paths at once, statistical experiments on the ISCAS89 benchmark set show the efficiency of the technique. In another set of experiments, the minimization of numbers of paths is compared to that of the number of nodes.
Keywords
VLSI; binary decision diagrams; circuit CAD; formal verification; integrated circuit design; integrated circuit modelling; logic CAD; minimisation; performance evaluation; BDD node number minimization; BDD path number minimization; SAT-solving; VLSI CAD applications; binary decision diagrams; circuit synthesis; formal verification; function expression memory requirement reduction; minimization algorithm efficiency; statistical benchmark testing; Application software; Binary decision diagrams; Boolean functions; Computer science; Data structures; Formal verification; Measurement standards; Minimization methods; Size measurement; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuits and Systems Design, 2002. Proceedings. 15th Symposium on
Print_ISBN
0-7695-1807-9
Type
conf
DOI
10.1109/SBCCI.2002.1137683
Filename
1137683
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