DocumentCode
2718500
Title
The Rambus memory system
Author
Gasbarro, James A.
Author_Institution
Rambus Inc., USA
fYear
1995
fDate
7-8 Aug 1995
Firstpage
94
Lastpage
96
Abstract
This paper describes a revolutionary new technology for building high-performance DRAM memory systems that operate up to 10 times faster than conventional systems. With only a 9-bit wide interface, devices are capable of transferring data at over 500 MBytes per second. This technology is implemented using standard CMOS process, packaging and printed circuit fabrication techniques, and is suitable for cost-sensitive volume applications
Keywords
CMOS technology; Clocks; Costs; Driver circuits; Graphics; Impedance; Master-slave; Microprocessors; Random access memory; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Technology, Design and Testing, 1995., Records of the 1995 IEEE International Workshop on
Conference_Location
San Jose, CA
Print_ISBN
0-8186-7102-5
Type
conf
DOI
10.1109/MTDT.1995.518088
Filename
518088
Link To Document