Title :
Yield and cost estimation for a CAM based parallel processor
Author :
Noghani, W.B. ; Jalowiecki, I.P.
Author_Institution :
Dept. of Electr. Eng., Brunel Univ., Uxbridge, UK
Abstract :
A comprehensive model is developed to estimate yield values for an associative string processor (ASP) chip which is populated with content addressable memory (CAM). The yield model comprises analysis of row and column redundancy strategies for the CAM combined with floor planning of the processor architecture. At the end, a cost model is developed, based on some actual fabrication costs, in order to optimise the processor according to a suitable figure of merit
Keywords :
circuit optimisation; content-addressable storage; costing; integrated circuit layout; integrated circuit yield; memory architecture; microprocessor chips; parallel architectures; parallel machines; redundancy; CAM based parallel processor; associative string processor chip; column redundancy strategies; content addressable memory; cost estimation; fabrication costs; figure of merit; floor planning; processor architecture; processor optimization; row redundancy strategies; yield value estimation; Application software; Application specific processors; Associative memory; CADCAM; Computer aided manufacturing; Computer architecture; Computer vision; Cost function; Logic arrays; Yield estimation;
Conference_Titel :
Memory Technology, Design and Testing, 1995., Records of the 1995 IEEE International Workshop on
Conference_Location :
San Jose, CA
Print_ISBN :
0-8186-7102-5
DOI :
10.1109/MTDT.1995.518091
