Invited paper: System-wide fault management based on IEEE P1687 IJTAG

Author

Jutman, A. ; Devadze, S. ; Aleksejev, J.

Author_Institution

Testonica Lab., Tallinn, Estonia

fYear

2011

fDate

20-22 June 2011

Firstpage

1

Lastpage

4

Abstract

Fault tolerance and fault management mechanisms are necessary means to reduce the impact of soft errors and wear out in electronic devices. The semiconductor products manufactured with latest and emerging processes are increasingly affected by these effects. The paper describes a new general scalable fault management architecture based on the latest upcoming DFT standard IEEE P1687 IJTAG. The standard allows to create an efficient and regular network for handling fault detection information as well as to manage test and system resources as a system-wide background process during the system operation.

Keywords

IEEE standards; fault tolerance; semiconductor device manufacture; semiconductor device reliability; DFT standard IEEE P1687 IJTAG; electronic devices; fault detection information; fault tolerance; semiconductor products; system-wide fault management mechanism; Fault tolerance; Fault tolerant systems; Instruments; Registers; Resilience; System-on-a-chip; Embedded Instrumentation; Failure Resilience; Fault Management; IEEE 1687; IJTAG;

fLanguage

English

Publisher

ieee

Conference_Titel

Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2011 6th International Workshop on

Conference_Location

Montpellier

Print_ISBN

978-1-4577-0640-0

Type

conf

DOI

10.1109/ReCoSoC.2011.5981520

Filename

5981520