Title :
A flexible gate array for high speed and high density applications
Author :
Gallia, Jim ; Landers, Robert ; Shaw, Ching-hao ; Blake, Terry ; Banzhaf, Wally
Author_Institution :
Semicond. Process & Design Center, Texas Instrum. Inc., Dallas, TX, USA
Abstract :
A scaleable gate array has been designed in half-micron CMOS for a wide range of high-speed and high-density applications. Transistor size and position within the basecell provide an efficient implementation of flip-flops, combinational gates, and memory. Design benchmarks have demonstrated 2700 gates/mm2 routed density in a 0.5 μm TLM CMOS gate array. Compared to previous 5 V 0.7 μm gate arrays, the new basecell provides a 2.5× density improvement, 30% speed-up, and 70% lower power. NAND-2 delays are 170 ps (FO=2, 3.3 V). Metal-programmable two-port SRAMs feature 3.9 ns typical access times. The new architecture has been implemented in a CMOS gate array family which offers up to 1.15 million available gates and 700 I/O positions
Keywords :
CMOS logic circuits; CMOS memory circuits; SRAM chips; application specific integrated circuits; logic arrays; 0.5 micron; 3.9 ns; combinational gates; flexible gate array; flip-flops; half-micron CMOS; high density applications; high speed applications; memory; metal-programmable two-port SRAM; scaleable gate array; Application software; CMOS technology; Circuit synthesis; Clocks; Delay; Flip-flops; Logic arrays; Logic gates; Routing; Telecommunications;
Conference_Titel :
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-2584-2
DOI :
10.1109/CICC.1995.518125
