Title :
CMOS gate array architecture for digital signal processing applications
Author :
Green, J.-M. ; Klar, H.
Author_Institution :
Inst. for Microelectron., Tech. Univ. Berlin, Germany
Abstract :
A CMOS gate array architecture for digital signal processing (DSP) is presented. The new structure takes into account the high degree of regularity of DSP datapaths and particularly supports the implementation of systolic arrays in connection with a pipelining scheme of one addition per half clock cycle. This reduces both the area and the power consumption by about 21% and 33%, respectively, compared to conventional gate arrays
Keywords :
CMOS logic circuits; digital signal processing chips; logic arrays; pipeline processing; systolic arrays; CMOS gate array architecture; DSP applications; digital signal processing; pipelining scheme; systolic arrays; Adders; CMOS process; Circuits; Clocks; Delay; Digital signal processing; Energy consumption; Latches; Pipeline processing; Systolic arrays;
Conference_Titel :
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-2584-2
DOI :
10.1109/CICC.1995.518128
