DocumentCode
2718825
Title
A two million gate 0.35 μm CMOS ASIC family
Author
Smith, Christina M.
Author_Institution
NEC Electron. Inc., Mountain View, CA, USA
fYear
1995
fDate
1-4 May 1995
Firstpage
17
Lastpage
19
Abstract
A two million gate gate array has been developed using a 0.35 μm CMOS sea-of-gates technology. In addition to the large integration capacity of the gate array, it also supports high speed I/O interface standards at voltages from 5 V to 1.4 V with a unique I/O power ring structure. Phase-locked loops (PLL) and clock skew management enable the technology to deliver speeds of up to 156 MHz at 3.3 V
Keywords
CMOS logic circuits; application specific integrated circuits; logic arrays; timing; 0.35 micron; 1.4 to 5 V; 156 MHz; CMOS ASIC family; I/O power ring structure; PLL; SOG technology; clock skew management; high speed I/O interface standards; phase-locked loops; sea-of-gates technology; Application specific integrated circuits; Clocks; Communication standards; Delay; Logic arrays; MOSFETs; Microprocessors; Phase locked loops; Protection; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location
Santa Clara, CA
Print_ISBN
0-7803-2584-2
Type
conf
DOI
10.1109/CICC.1995.518129
Filename
518129
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