Title :
How to generate high quality tests for digital systems
Author :
Ubar, R. ; Aarna, M. ; Kruus, H. ; Raik, Jaan
Author_Institution :
Tallinn Tech. Univ., xx, Estonia
Abstract :
A uniform approach for modeling faults and structure of digital systems is presented. Physical defects are modelled as parameters in generic Boolean differential equations. Solutions of the equations give the conditions called functional fault model at which defects are locally activated. The functional fault model can be regarded as a uniform interface for mapping faults from one system level to another, helping to carry out hierarchical test generation. For representing the system decision diagrams (DD) are used. Binary DDs represent logic level whereas register level DDs represent higher-level structures. Experiments have shown the feasibility and efficiency of the hierarchical method compared to the classical one-level stuck-at fault based approaches.
Keywords :
Boolean functions; binary decision diagrams; differential equations; fault simulation; integrated logic circuits; logic simulation; logic testing; BDD; binary decision diagrams; digital system quality tests; faults mapping; faults modeling; functional fault model; generic Boolean differential equations; hierarchical test generation; logic level; one level stuck-at fault; physical defects; register level decision diagrams; Boolean functions; CMOS integrated circuits; Circuit faults; Circuit testing; Digital systems; Equations; Integrated circuit modeling; Semiconductor device modeling; System testing; Tires;
Conference_Titel :
Semiconductor Conference, 2004. CAS 2004 Proceedings. 2004 International
Print_ISBN :
0-7803-8499-7
DOI :
10.1109/SMICND.2004.1403048