A study on fine granular fault tolerance methodologies for FPGAs

Single Event Upsets will gain more importance for future nanoscale architectures, which will be more sensitive to such effects. Especially for domains like space applications robust redundany methodologies are needed to make use of these new architectures. In this paper we study fine grain redundancy methodologies which can be used to construct high robust designs. Our basic approach is to localize the fault tolerance structure to a fine grain view. We then show two methodologies which are suitable for FPGAs. The methodologies are similar to Triple Modular Redundancy (TMR) which is a widely used approach for mitigating upsets and failures. However for new device generations simply replicating complete systems in TMR manner may not be sufficient anymore especially in harsh environments, such as space applications. We integrate both approaches into standard FPGA tool flows thereby introducing redundancy automatically without user interaction.