Study and modeling of a new configuration of an optical network on chip (ONOC) using FDTD

The increasing need to reduce power consumption and interconnection complexity in optical network on chip requires new configurations and strategies to interconnect cores in one chip. In this paper, we study a new configuration for an optical router on chip ≪ROTAR≫. In this router, the number of microrings was reduced to 4, allowing 30% reduction of power consumption compared to Huaxi Gu et al. We study waveguide losses at crossing, bends and resonant rings using the numerical method FDTD. Then, we propose an algorithm to perform a global estimation of all type of losses in our optical network on chip, assuming 1mm² area and use of 8*8 routers. Using the Fat-H-Tree topology, we can reduce the number of routers interconnecting 64 cores, compared to the configuration proposed by Huaxi Gu et al. We use GaAs as a substrate to facilitate the integration of optoelectrical devices and silicon waveguides (refraction index = 3,5) surrounded by a layer of silica (1,43) to achieve a strong field confinement in the waveguide. The use of such routers in OnoC has several benefits such as a static and simple routing algorithm and more interconnection capacity compared to λ-router.