A scaled 0.6 μm high speed PLD technology using single-poly EEPROM´s

Author

Adan, A.O. ; Smolen, R. ; Tokuyama, N. ; Ohmi, T. ; Wright, P. ; Madurawe, R. ; Kagisawa, A. ; Gregoire, F.

Author_Institution

VLSI Res. & Dev. Lab., Sharp Corp., Nara, Japan

fYear

1995

fDate

1-4 May 1995

Firstpage

55

Lastpage

58

Abstract

A 0.6 μm CMOS single-polycide, double-metal, EEPROM technology for Programable Logic Device applications is described. A channel-stop implantation through an optimized LOCOS, and a compensated P-well profile at the N+/P junction, results in an aggressive 1.5 μm field isolation pitch that satisfies the 12.5 V high-voltage requirement. The FN tunneling currents allow on-chip high-voltage generation from a single power supply for ISP applications. The EPM7032A and EPM7128E PLD products propagation delay time of 4.4 nsec and 6.8 nsec respectively, are the fastest reported at 32 and 128 macro-cell densities

Keywords

CMOS logic circuits; EPROM; cellular arrays; integrated circuit technology; ion implantation; programmable logic devices; tunnelling; 0.6 micron; 12.5 V; 4.4 ns; 6.8 ns; CMOS; FN tunneling currents; ISP applications; N+/P junction; Sharp EPM7032A; Sharp EPM7128E; channel-stop implantation; compensated P-well profile; field isolation pitch; high speed PLD technology; high-voltage requirement; macro-cell densities; on-chip high-voltage generation; optimized LOCOS; propagation delay time; single-poly EEPROM; single-polycide double-metal technology; CMOS process; Delay; Dielectric losses; EPROM; Implants; MOSFET circuits; Macrocell networks; Tin; Tunneling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-2584-2

Type

conf

DOI

10.1109/CICC.1995.518136

Filename

518136