Fast parasitic extraction for substrate coupling in mixed-signal ICs

Techniques for the fast extraction of substrate resistances in mixed-signal integrated circuits are presented. For a given process, a simple analytical model for point-to-point substrate impedance is determined during a preprocessing stage. A hierarchical extraction strategy is then employed using this simple analytical model in conjunction with a delimitation technique to quickly determine resistive coupling through the substrate on a cell-by-cell basis. The extraction procedure yields a resistive netlist which when simulated along with necessary parasitic capacitances and the circuit itself determines any performance limitations in the design due to substrate coupling. The extraction procedure has been used in the verification and redesign of a triple 8-bit video A/D converter IC for substrate-noise problems