A methodology for rapid estimation of substrate-coupled switching noise

In this paper we present a methodology for rapid estimation of substrate coupled switching noise in mixed-signal chips. This methodology differs from existing approaches in that it does not require full chip, SPICE level transient or frequency domain simulations or long user-specified test vectors at the chip I/O. Instead, it relies on power dissipation data available from system-level power estimators and determines an estimate of the substrate coupled switching noise profile on the chip-substrate. This method trades off the accuracy available in existing approaches for improved execution times and significantly simpler user-inputs. Thus, this methodology is useful when rough estimates of substrate coupled switching-noise are adequate, for example, during manual or automatic system-level mixed-signal floorplanning