A 250-MHz skewed-clock pipelined dual-port embedded DRAM

Author

Heshami, Mehrdad ; Wooley, Bruce A.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

fYear

1995

fDate

1-4 May 1995

Firstpage

143

Lastpage

146

Abstract

A special-purpose dual-port dynamic memory suitable for use in a variety of digital switching and signal processing applications is described. The memory design is based on a dual-port three-transistor (3T) cell that occupies less than half the area of a conventional dual-port SRAM cell. Hamming error correction coding (ECC) is used to improve the memory´s immunity to soft errors, as well as enhance its fabrication yield. Skewed-clock pipelining permits operation at clock rates as high as 250 MHz, and a compact low power sense amplifier circuit allows the use of a wide data bus to increase the memory´s bandwidth

Keywords

DRAM chips; Hamming codes; clocks; error correction codes; memory architecture; pipeline processing; two-port networks; 250 MHz; Hamming error correction coding; clock rates; digital switching; dual-port three-transistor cell; fabrication yield; low power sense amplifier circuit; memory bandwidth; pipelined dual-port embedded DRAM; signal processing applications; skewed-clock pipelining; soft error immunity; wide data bus; Circuits; Clocks; Digital signal processing; Error correction; Error correction codes; Fabrication; High power amplifiers; Operational amplifiers; Pipeline processing; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-2584-2

Type

conf

DOI

10.1109/CICC.1995.518154

Filename

518154