A 500-MHz, 0.4-μm CMOS, 32-word by 32-bit 3-port register file

Author

Nomura, Masahiro ; Yamashina, Masakazu ; Suzuki, Kazumasa ; Izumikawa, Masaiiori ; Igura, Hiroyulci ; Abiko, Hitoshi ; Okabe, Kazuhiro ; Ono, Atsuki ; Nakayama, Takashi ; Yamada, Hachiro

Author_Institution

NEC Corp., Sagamihara, Japan

fYear

1995

fDate

1-4 May 1995

Firstpage

151

Lastpage

154

Abstract

A 0.4-μm CMOS, 32-word by 32-bit 3-port register file has been developed for use in high speed microprocessors. It features a high-speed-oriented memory structure, low threshold voltage nMOS FETs, and a short read-precharge design. This register file has been designed for use within a small-skew clock-distribution processor datapath, and experimental results show it to be capable of 500-MHz register file operations

Keywords

CMOS digital integrated circuits; clocks; microprocessor chips; multiport networks; 0.4 micron; 32 bit; 32-word by 32-bit; 500 MHz; 500-MHz, 0.4-μm; CMOS; high speed microprocessors; memory structure; nMOS FETs; register file operations; short read-precharge design; small-skew clock-distribution processor datapath; three-port register file; threshold voltage; Circuits; Clocks; Delay; FETs; MOS devices; Pulse generation; Pulse inverters; Pulse width modulation inverters; Registers; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-2584-2

Type

conf

DOI

10.1109/CICC.1995.518156

Filename

518156