DocumentCode
2719390
Title
The 8-bit Parallel CRC-32 Research and Implementation in USB 3.0
Author
Wu, Ying ; Qiu, Yuehong
Author_Institution
Xi´´an Inst. of Opt. & Precision Mech., Xi´´an, China
fYear
2012
fDate
11-13 Aug. 2012
Firstpage
1079
Lastpage
1082
Abstract
This thesis proposed 8-bit parallel CRC-32 in order to meet the high throughput of USB3.0. The highest speed of USB3.0 reaches 5G bps. Firstly, we researched the Data Packet structure and the principles of the CRC-32 in the USB3.0 Specification. Secondly, deduced the equation of the 8-bit input data and the CRC-32. Finally, implemented the CRC-32 coding and decoding by the verilog HDL, verified the correctness of the design. The 8-bit parallel CRC-32 can process 8 bits every clock cycle.
Keywords
cyclic redundancy check codes; decoding; hardware description languages; peripheral interfaces; 8-bit input data; 8-bit parallel CRC-32; CRC-32 coding; CRC-32 decoding; USB 3.0; clock cycle; cyclic redundancy check; data packet structure; design correctness verification; hardware description languages; universal serial bus; verilog HDL; Clocks; Decoding; Encoding; Equations; Hardware design languages; Payloads; Universal Serial Bus; 8-bit parallel; Cyclic Redundancy Check-32; Universal Serial bus 3.0;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Science & Service System (CSSS), 2012 International Conference on
Conference_Location
Nanjing
Print_ISBN
978-1-4673-0721-5
Type
conf
DOI
10.1109/CSSS.2012.273
Filename
6394511
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