Title :
Circuit technique for skew-free clock distribution
Author :
Sutoh, Hiroki ; Yamakoshi, Kimihiro ; Ino, Masayuki
Author_Institution :
NTT LSI Labs., Atsugi, Japan
Abstract :
This paper describes a low-skew clock distribution technique for multiple targets using an automatic skew-compensation circuit. Using this technique keeps clock skew among multiple targets below the resolution time of the variable delay lines without any manual adjustment. Measured results show that the initial clock skew of 0.9 ns is cancelled automatically and 30 ps clock skew is achieved at a clock frequency of up to 250 MHz with 60 ps clock jitter
Keywords :
clocks; delay lines; 250 MHz; 30 ps; automatic skew-compensation circuit; clock distribution; multiple targets; variable delay lines; CMOS technology; Clocks; Delay lines; Frequency measurement; Integrated circuit interconnections; Jitter; Laboratories; Large scale integration; Propagation delay; Voltage control;
Conference_Titel :
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-2584-2
DOI :
10.1109/CICC.1995.518159
