Efficient DSP design for vocoder application

Author

Yoo, H.Y. ; Kim, Jonghoon J. ; Byun, K.J. ; Han, K.C. ; Kim, Duk Kyung ; Kim, J.J. ; Lee, H.B. ; Bae, M.J.

Author_Institution

Semicond. Div., ETRI, Taejon, South Korea

fYear

1995

fDate

1-4 May 1995

Firstpage

189

Lastpage

192

Abstract

Vocoder is a key component of the digital cellular system. A DSP architecture which supports the direct and immediate addressing modes in one instruction cycle, combined with a RISC-style instruction set, turns out to be effective for vocoder implementation in terms of proper performance and lower power consumption requirements. By adopting a dual bank memory system and an efficient ALU bus scheme, two 16-bit operand access and ALU operation can be executed simultaneously. Improved implementation methods applicable to CELP type vocoder in which the pitch search is performed by the analysis-by-synthesis, are also presented

Keywords

CMOS digital integrated circuits; cellular radio; digital radio; digital signal processing chips; linear predictive coding; reduced instruction set computing; speech coding; vocoders; 0.8 micron; 320 mW; 4.5 to 5.5 V; 40 MIPS; 80 MHz; ALU bus scheme; CELP type; DSP architecture; DSP design; RISC-style instruction set; analysis-by-synthesis; digital cellular system; dual bank memory system; pitch search; power consumption requirements; vocoder application; Algorithm design and analysis; Data mining; Decoding; Delay effects; Digital signal processing; Encoding; Energy consumption; Linear predictive coding; Multiaccess communication; Vocoders;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-2584-2

Type

conf

DOI

10.1109/CICC.1995.518165

Filename

518165