Title :
A 14-bit 500 kHz delta-sigma ADC with 16 times oversampling
Author :
Baîrd, Rex T. ; Fiez, Terri S.
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
Abstract :
A 14-bit 500 kHz delta-sigma ADC is described that uses an oversampling ratio of only 16. A fourth-order embedded architecture is used along with a 4-bit quantizer to achieve this performance. Although previously believed to be unstable, it is shown that with proper design a robust design may be obtained. This is the lowest oversampling ratio for this resolution and bandwidth achieved to date
Keywords :
CMOS integrated circuits; sigma-delta modulation; switched capacitor networks; 14 bit; 500 kHz; delta-sigma ADC; fourth-order embedded architecture; oversampling; quantizer; Application specific integrated circuits; Bandwidth; Calibration; Delay; Delta modulation; Dynamic range; Limit-cycles; Multi-stage noise shaping; Quantization; Stability;
Conference_Titel :
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-2584-2
DOI :
10.1109/CICC.1995.518167
