DocumentCode
2719679
Title
A 350-MS/s 3.3-V 8-bit CMOS D/A converter using a delayed driving scheme
Author
Kohno, Hiroyuki ; Nakamura, Yasuyuki ; Kondo, Atsuhito ; Amishiro, Hiroyuki ; Miki, Takahiro ; Okada, Keisuke
Author_Institution
Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
fYear
1995
fDate
1-4 May 1995
Firstpage
211
Lastpage
214
Abstract
This proceeding describes a 350-MS/s 8-bit CMOS D/A converter with 3.3-V power supply. A current source with a delayed driving scheme is developed. This driving scheme reduces fluctuation of internal node voltage of the current source and high-speed switching is realized. Two stages of latches are inserted into the matrix decoder for reducing glitch energy and for enhancing decoding speed. The D/A converter is fabricated in a 0.5-μm CMOS process. Its settling time is less than 2.4 ns and it successfully operates at 350 MS/s
Keywords
CMOS integrated circuits; analogue-digital conversion; delay circuits; driver circuits; 0.5 micron; 3.3 V; 8 bit; CMOS DAC; D/A converter; current source; decoding speed; delayed driving scheme; high-speed switching; matrix decoder; Decoding; Degradation; Delay; Fluctuations; Large scale integration; Latches; Matrix converters; Power supplies; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location
Santa Clara, CA
Print_ISBN
0-7803-2584-2
Type
conf
DOI
10.1109/CICC.1995.518170
Filename
518170
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