A 10 bit low-power CMOS D/A converter with on-chip gain error compensation

Author

Henriques, Bernardo G. ; Kananen, Kari ; Franca, J.E. ; Rapeli, Juha

Author_Institution

Integrated Circuits & Syst. Group, IST Center for Micro Syst., Portugal

fYear

1995

fDate

1-4 May 1995

Firstpage

215

Lastpage

218

Abstract

This paper describes a 10-bit, 500 kHz, low-power steering-current CMOS D/A converter for portable communications. A triple-segmented architecture is used to improve the linearity while minimizing the circuit area and gain error compensating circuitry is employed to correct for full-scale errors. The prototype chip fabricated in a 1.2 μm standard CMOS technology occupies less than 0.45 mm² and consumes less than 2.4 mW for a 1 V output swing at 5 V supply. Full-scale voltage errors due to chip-to-chip variations are better than ±3% and below ±43 ppm/°C for temperature drifts in the range -30°C to +85°C

Keywords

CMOS integrated circuits; digital-analogue conversion; error compensation; error correction; -30 to 85 C; 1.2 micron; 10 bit; 2.4 mW; 5 V; 500 kHz; D/A converter; full-scale error correction; gain error compensating circuitry; low-power CMOS DAC; onchip gain error compensation; portable communications; steering-current; triple-segmented architecture; CMOS technology; Circuits; Error compensation; Error correction; Linearity; Matrix converters; Resistors; Switches; Temperature distribution; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-2584-2

Type

conf

DOI

10.1109/CICC.1995.518171

Filename

518171