Accurate MOS device hot carrier models for VLSI reliability simulation

This paper describes a Spice-compatible circuit reliability simulation model of submicron LDD MOS devices. It incorporates an accurate hot carrier model of the degraded MOSFET characteristics under long term operations, which includes a drain current model and a substrate current model. The drain current reduction is modeled as mobility degradation due to interface states enhanced scattering. The substrate current model is developed based on a new effective electric field concept which shows a significant improvement to the conventional local field model. By characterizing the time-dependence of the device parameters, hot carrier I-V model can be obtained. Comparison of the modeled results with experiment shows excellent match for a wide range of device channel length, bias conditions and stress time. Moreover, the reliability simulator that we developed allows prediction of lifetime or aging of a device or circuit in VLSI design