DocumentCode :
2719852
Title :
Accurate parasitic resistance extraction for interconnection analysis
Author :
Wang, Yucheng ; Overhauser, David ; Basel, Mark
Author_Institution :
Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
fYear :
1995
fDate :
1-4 May 1995
Firstpage :
255
Lastpage :
258
Abstract :
With the further scaling down of feature sizes, parasitic resistance is becoming more important for interconnection analysis. Previous resistance modeling and extraction methods either sacrifice too much speed for accuracy or sacrifice too much accuracy for speed. Neither of which is sufficient for effective interconnection analysis. In this paper we present a parasitic resistance extraction methodology which is both fast and accurate. The strategy is to fracture the resistive polygons into regions of different electromagnetic complexity and then use different algorithms to solve each region of complexity. Experimental results show that extracted resistances are within 5% of pure FEM resistance extraction for most test cases and within 10% for a few extreme cases while performing the extraction only about an order of magnitude slower than the path-finding parasitic resistance extraction technique
Keywords :
circuit analysis computing; digital simulation; integrated circuit design; integrated circuit interconnections; IC design; circuit simulation; delays; design verification; electromagnetic complexity; feature sizes; interconnection analysis; parasitic resistance extraction; resistive polygons; Circuit simulation; Circuit testing; Contacts; Delay; Electric resistance; Finite element methods; Integrated circuit interconnections; Nonlinear equations; Parameter extraction; Parasitic capacitance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-2584-2
Type :
conf
DOI :
10.1109/CICC.1995.518180
Filename :
518180
Link To Document :
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