Title :
Optimal and efficient buffer insertion and wire sizing
Author :
Lillis, John ; Cheng, Chung-Kuan ; Lin, Ting-Ting Y.
Author_Institution :
Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
Abstract :
We present optimal solutions to the following problems: (1) post-layout buffer insertion, (2) wire-sizing and (3) simultaneous buffer insertion and wire-sizing. We optimize a practical objective function: required arrival time. To the best of our knowledge, this work represents the first sub-exponential algorithms for these problems. In experiments, we observe substantial improvements over previous results for buffer insertion, and up to 25% improvement in delay by wire-sizing
Keywords :
buffer circuits; circuit layout; circuit optimisation; timing; arrival time; buffer insertion; circuit layout; delay; optimization; sub-exponential algorithms; wire sizing; Capacitance; Computer science; Delay; Libraries; Optimization methods; Polynomials; Routing; Space technology; Timing; Wire;
Conference_Titel :
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-2584-2
DOI :
10.1109/CICC.1995.518181
