Low power IC clock tree design

Author

Pullela, Satyamurthy ; Menezes, Noel ; Pillage, Lawrence T.

Author_Institution

Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

fYear

1995

fDate

1-4 May 1995

Firstpage

263

Lastpage

266

Abstract

When reliability to process variations becomes an important issue, wires in the clock-tree must be made extremely wide to limit the process skew to a specified tolerable value. Due to the resultant increase in the overall capacitance, the power dissipation in clock-net is dramatically increased. We demonstrate that in spite of buffer mismatches and an additional component of power dissipation due to their short-circuit currents, the clock tree power can be significantly reduced by buffer insertion given the constraint on allowable process-variation dependent skew and maximum current densities (electromigration)

Keywords

buffer circuits; clocks; integrated circuit design; integrated circuit reliability; trees (mathematics); buffer insertion; capacitance; current densities; electromigration; low power IC clock tree design; power dissipation; process variations; reliability; short-circuit currents; skew; wires; Capacitance; Clocks; Contracts; Current density; Delay; Electromigration; Power dissipation; Power integrated circuits; Voltage; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-2584-2

Type

conf

DOI

10.1109/CICC.1995.518182

Filename

518182