Title :
PCHECK: a delay analysis tool for high performance LSI design
Author :
Miki, Yoshio ; Abe, Masahide ; Ogawa, Yasushi
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
This paper describes new problems in delay analysis for high-performance LSI design and presents a static delay analysis tool PCHECK. PCHECK is characterized by (1) a new critical path trace algorithm for avoiding the error caused by signal transient time, (2) a precise delay calculation model for resistive shielding and (3) parallel delay calculation on networked workstations. Experimental results show that the delay calculation error in the worst case is less than 20 ps and that the speed improvement when using 20 workstations is over 17 times that for a single processor
Keywords :
circuit CAD; critical path analysis; delays; integrated circuit design; large scale integration; PCHECK; critical path trace algorithm; delay calculation model; high performance LSI design; networked workstations; parallel delay calculation; resistive shielding; signal transient; static delay analysis tool; Algorithm design and analysis; Capacitance; Circuit simulation; Clocks; Delay effects; Large scale integration; Logic devices; Logic gates; Performance analysis; Wire;
Conference_Titel :
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-2584-2
DOI :
10.1109/CICC.1995.518183
