A high-speed, high-resolution analog front end for digital subscriber line applications

Author

Shariatdoust, R. ; Lakshmikumar, K. ; Moon, U. ; Fetterman, H.S. ; Sankaran, M. ; Sherry, D. ; Kumar, J. ; Daubert, S.

Author_Institution

AT&T Bell Labs., Allentown, PA, USA

fYear

1995

fDate

1-4 May 1995

Firstpage

289

Lastpage

292

Abstract

A 5 V CMOS chip providing the D/A, A/D, filter, and a programmable gain amplifier (PGA) for HDSL and ADSL is described. The chip includes 12-bit, 10 Msample/sec converters, filters, and a PGA having 48 dB gain with 1.7 MHz bandwidth. This chip is used in an E1-rate (2.048 Mbps) ADSL transceiver achieving a bit error rate of less than 10^-9 over 5.4 km of 0.4 mm twisted copper wire

Keywords

CMOS analogue integrated circuits; analogue-digital conversion; digital-analogue conversion; subscriber loops; transceivers; twisted pair cables; 1.7 MHz; 12 bit; 2.048 Mbit/s; 48 dB; 5 V; 5.4 km; A/D convertor; ADSL; CMOS chip; D/A convertor; E1-rate transceiver; HDSL; analog front end; asymmetric digital subscriber line; bit error rate; digital subscriber line applications; programmable gain amplifier; twisted copper wire; Calibration; Circuits; Copper; DSL; Digital filters; Electronics packaging; Finite impulse response filter; Latches; Transceivers; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-2584-2

Type

conf

DOI

10.1109/CICC.1995.518188

Filename

518188