DocumentCode :
2720058
Title :
A 2-V, 2-GHz low-power direct digital frequency synthesizer chip set for wireless communication
Author :
Yamagishi, Akihiro ; Ishikawa, Masayuki ; Tsukahara, Tsuneo ; Date, Shigeru
Author_Institution :
NTT LSI Labs., Kanagawa, Japan
fYear :
1995
fDate :
1-4 May 1995
Firstpage :
319
Lastpage :
322
Abstract :
A 2-GHz direct digital frequency synthesizer (DDFS) chip-set that operates at the very low supply voltage of 2 V is introduced. This microwave DDFS, the first to be fully implemented using LSI technologies, consists of a CMOS DDFS-LSI with an internal 10-bit DAC and Si-bipolar up-converters. To achieve both high purity and low power dissipation, we use a distortion-free up-conversion architecture and an efficient ROM output bit-width reduction technique. The synthesizer achieves a wide spurious-free dynamic range of 53.7 dB and a low power dissipation of less than 160 mW at 2 GHz
Keywords :
CMOS integrated circuits; MMIC frequency convertors; application specific integrated circuits; digital-analogue conversion; direct digital synthesis; frequency synthesizers; large scale integration; 10 bit; 160 mW; 2 GHz; 2 V; CMOS; DAC; LSI technologies; ROM output bit-width reduction; distortion-free up-conversion architecture; low-power direct digital frequency synthesizer; microwave DDFS; power dissipation; spurious-free dynamic range; up-converters; wireless communication; Band pass filters; CMOS technology; Frequency synthesizers; Laboratories; Large scale integration; Power dissipation; Power harmonic filters; Read only memory; Threshold voltage; Wireless communication;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-2584-2
Type :
conf
DOI :
10.1109/CICC.1995.518194
Filename :
518194
Link To Document :
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