Title :
Realistic worst-case SPICE file extraction using BSIM3
Author :
Chen, James C. ; Hu, Chenming ; Liu, Zhihong ; Ko, Ping K.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
In this paper, a methodology for generating worst-case SPICE files is presented. This methodology is based upon the identification and evaluation of circuit building blocks within a design. Correlations between these block are determined for a specific circuit variable. The results show there is a high degree of correlation between NAND, NOR, inverter logic gates and NAND gates implemented in Complementary Pass Transistor Logic (CPL) with regards to speed and power dissipation. A method of resolving multiple SPICE files is also presented which produces a realistic prediction of circuit performance
Keywords :
SPICE; circuit analysis computing; logic circuits; logic gates; BSIM3; NAND gates; NOR gates; circuit building blocks; circuit performance prediction; complementary pass transistor logic; inverter logic gates; power dissipation; worst-case SPICE file extraction; Circuit optimization; Circuit simulation; Data mining; Logic circuits; Logic gates; Predictive models; Pulse inverters; Ring oscillators; SPICE; Tiles;
Conference_Titel :
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-2584-2
DOI :
10.1109/CICC.1995.518206
