Statistical worst-case simulation for CMOS technology

This paper presents a methodology for statistical worst-case simulation which accounts for the effects of statistical fluctuations in IC manufacturing processes. The inclusion of important SPICE model parameter correlations and the application of second order regression models give both realistic and more accurate worst-case parameter sets. Furthermore, a realistic prediction of circuit performance spread as well as an indication of the key process parameters that need to be monitored and controlled, are provided. The methodology consists of statistical techniques such as Principal Component Analysis and Box-Behnken designs. Finally, the principle of nonsense limits is incorporated to improve the accuracy of the predictions