EYE: a tool for measuring the defect sensitivity of IC layout

The development of new aggressively target IC processes brings new challenges to the design and fabrication of high yielding ICs. As much as 50% of yield loss in digital ICs can be attributed to the metallisation stages of fabrication. This can be a particular problem when new process technologies such as multilevel interconnect are being introduced. This paper addresses the problem of design for manufacture of IC layout by presenting a tool that enables the measurement of critical area and hence layout defect sensitivity. The EYE (Edinburgh Yield Estimator) tool has two main uses, yield prediction and the comparison of defect sensitivities of place and routing algorithms. Its use as a tool to measure and optimise the defect sensitivity and hence the manufacturability of the IC layout produced by automated routing algorithms will be explored in this paper