Sensitivity of MOS transistor mismatch to device dimensions and suggestions on how to improve matching performance

In this work, an investigation of the effects of device geometry on MOS transistor mismatch is undertaken. In addition a parameter extraction scheme suitable for mismatch measurements is described which provides greater repeatability than existing extraction schemes. Improvement of mismatch with decreasing gate oxide thickness is well documented, as is the relationship between mismatch and layout area, i.e. mismatch α 1/√(WL). However, the measurements presented here will show that the matching performance is related not only to the gate area, but also individually to the effective channel length L and width W. Hence, for a given layout area (WL), the mismatch is significantly altered by varying the aspect ratio (W/L). Measurements were taken from both NMOS and PMOS devices in a 1 μm and a 0.8 μm process. We show threshold voltage mismatch measurements for PMOS devices manufactured on a 1 μm process. The W/L=12.5/1 device and the W/L=2.5/5 device have the same area, however, the W/L=2.5/5 device has approximately 40% better matching than the W/L=12.5/1 device. It will be shown that for threshold voltage mismatch, this may be explained by the influence of short and narrow channel effects on the bulk charge term in the threshold voltage equation. Based upon the findings in this work, recommendations for the improvement of MOS transistor mismatch are proposed. Applications where mismatch between transistors is critical to device performance include digital to analog converters and sense amplifiers from DRAM arrays