Title :
A novel scheme of FLEX pager design
Author :
Xiaojian, Lu ; Weidong, Li ; Song, Li ; Jing, Wang
Author_Institution :
Dept. of Electron. Eng., Tsinghua Univ., Beijing, China
Abstract :
FLEX protocol is the de-facto standard of the high speed paging system in China and the USA. Most FLEX pager designs consist of three parts: RF module, MCU and FLEX decoder. This paper describes a new design scheme in which the MCU and FLEX decoder functions are accomplished by an ASIC based on a structure of MCU+DSP. In order to store the MCU and DSP program in the limited memory buffer on the RISC in this design, a module mode program scheme and an ameliorated BCH decoding algorithm are adopted. The FPGA testing circuit proves that this new scheme can complete the basic FLEX pager function in the required time interval. Besides this, through downloading different firmware and software to this ASIC, two-way pager, MP3 player and digital recorder functions can also be implemented
Keywords :
BCH codes; application specific integrated circuits; decoding; digital signal processing chips; field programmable gate arrays; paging communication; reduced instruction set computing; ASIC; China; DSP; FLEX decoder; FLEX pager design; FLEX protocol; FPGA testing circuit; MCU; MP3 player; RF module; RISC; USA; ameliorated BCH decoding algorithm; de-facto standard; digital recorder; firmware; high speed paging system; memory buffer; module mode program scheme; software; two-way pager; Algorithm design and analysis; Application specific integrated circuits; Buffer storage; Circuit testing; Decoding; Digital signal processing; Field programmable gate arrays; Protocols; Radio frequency; Reduced instruction set computing;
Conference_Titel :
Communication Technology Proceedings, 2000. WCC - ICCT 2000. International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7803-6394-9
DOI :
10.1109/ICCT.2000.890979
