A novel scheme of FLEX pager design

FLEX protocol is the de-facto standard of the high speed paging system in China and the USA. Most FLEX pager designs consist of three parts: RF module, MCU and FLEX decoder. This paper describes a new design scheme in which the MCU and FLEX decoder functions are accomplished by an ASIC based on a structure of MCU+DSP. In order to store the MCU and DSP program in the limited memory buffer on the RISC in this design, a module mode program scheme and an ameliorated BCH decoding algorithm are adopted. The FPGA testing circuit proves that this new scheme can complete the basic FLEX pager function in the required time interval. Besides this, through downloading different firmware and software to this ASIC, two-way pager, MP3 player and digital recorder functions can also be implemented