A high performance processor switch based architecture for fault tolerant computing

A novel fault tolerant switch concept in the context of fault tolerant network architecture is discussed. This intelligent switch provides a non-blocking transmission path for all of its resources of the network architecture such as processor buses, disk subsystems, and its peripherals. In addition, it incorporates concurrent error detection, time-out mechanisms and a sophisticated error detecting protocol between the switch matrix and the resource management units to detect the hardware errors. Upon detection of the error, several recovery techniques are provided to ensure continuous operation of the system. Additional features of the network architecture for supporting high performance applications include concurrent channel access and priority channel service. The studies show that the fully connected network which supports both graceful degradation and standby sparing techniques exhibits excellent reliability performance and throughput